1. Field of the Invention
The present invention relates to a method of operating a successive approximation register (SAR) type analog-to-digital converter (ADC) and to an analog-to-digital converter configured to use the method.
2. Description of the Related Art
FIG. 1 shows a conventional SAR-type single-ended ADC 10 comprising an array of binary weighted capacitors, namely an array formed of N capacitors C0 . . . Cj . . . CN-1 with capacitances varying according to a factor 2j, where j varies from 0 to N-1. An additional capacitor Cx, with the same capacitance as the smallest capacitor (C0) of the array, is provided to obtain an overall array capacitance which is exactly twice the capacitance of the largest capacitor (CN-1) of the array. Each capacitor of the array has an electrode connected to a common node NS and another electrode connected, through a respective switch SINj . . . SREFj . . . SGNDj . . . , either to an input terminal 11 to receive a voltage VIN (referred to ground) to be converted, or to a first reference terminal to receive a first reference voltage VREF (referred to ground), or to a second reference terminal to receive a second reference voltage, in this example ground. The node NS is connected to the inverting input of an operational amplifier 20, which has a non-inverting input connected to ground and operates as a comparator. The output OUT of the operational amplifier is fed back to the inverting input through a switch SWR. The comparator output OUT is also connected to a SAR control logic circuit 25. The SAR control logic circuit 25 has a first output terminal at which the digital output code is produced and further output terminals that provide binary control signals B0 . . . Bj . . . BN-1, CARVIN and BR to the drivers (broadly indicated DRV) of the switches SINj . . . SREFj . . . SGNDj . . . and to the switch SWR. An analysis of the logic gates which form the switch drivers DRV shows that switches SREFj and SGNDj are equivalent to a two-way switch which is opened or closed depending on the binary value of bit Bj to connect the capacitor Cj either to VREF or to ground. The binary signal CARVIN controls switch SINj to open or close a connection of capacitor Cj to VIN and inhibits the closure of both switches SREFj and SGNDj when switch SINj is on.
The operation principle is that typical of an SAR-type ADC. First, signal BR closes switch SWR to connect node NS to a virtual ground and signal CARVIN closes switches SIN0 . . . SINj . . . SINN-1 This causes all the array capacitors to be charged to the voltage VIN to be converted. Then, switch SWR is opened, so that node NS remains floating, and the SAR control logic 25 controls, through the binary signals BO-BN-1, the switches associated with the capacitors to selectively couple each capacitor of the array to either one of the first and second voltage reference terminals (VREF,ground) according to the SAR technique. As a result of this operation step, node NS is brought to voltage:       V    NS    =            -              V        IN              +                  ∑                  j          =          1                N            ⁢              xe2x80x83            ⁢                        (                                    V              REF                                      2              j                                )                ·                  b          j                    
where bj indicates the binary value of the j-th bit (associated with capacitor Cj of the array). The operational amplifier 20 reads the sign of the voltage at node NS and outputs a corresponding digital signal. The control logic 25 is responsive to this digital signal to determine the value of the current bit of the output code and provides the capacitor array with a digital code for controlling the capacitor switches SREFj, SGNDj in the subsequent operation step. After the last step, on the SAR control logic output there is the digital code (OutputCode) corresponding to VIN.
A basic requirement for a correct design of a SAR-type ADC is a substantial equality of the dynamic range, i.e., the maximum swing of the voltage signal to be converted, and the Full Scale Range (FSR), i.e., the difference between the internal reference voltages (VREF and ground in the circuit of FIG. 1). If an optimum performance is required, the voltage signal to be converted should not be too high so as to be cut off, which would cause a conversion saturation error, and not too much lower than the FSR, otherwise the resolution of the converter would not be used at the best.
Usually, when the signal dynamic range is known, the designer implements a reference voltage generator capable of providing an FSR at least as large as the dynamic range.
This approach brings about two problems. First, the trend to the supply voltage reduction in the integrated circuit design and the requirement of providing a proper stable biasing of the operational amplifiers which generate the voltage references limit severely the maximum obtainable FSR. Second, it is often required to handle input voltage signals having different dynamic ranges. In this case, the FSR should be adjusted to each input dynamic range if the maximum resolution is to be obtained; this solution, however, is unpractical and generally difficult, if not impossible, in its implementation. Other known solutions keep a fixed FSR and provide networks for down-scaling the input signal before it is applied to the capacitor array, as shown in FIGS. 2 and 3.
FIG. 2 shows an ADC 10 identical to that of FIG. 1 with a down-scaling network 26 implemented with a simple resistor voltage divider. Four resistors R0, R1, R2, R3 are shown in series between an input terminal 27 and ground. The input terminal 27 and three taps of the divider can be selectively connected to the input terminal 11 of the converter 10 through a switch SWS controlled by a selection register 28. If the FSR at the input 11 of the converter 10 is known and the different dynamic ranges of the input signals are known, the divider can be easily designed to provide down-scaled replicas of the input voltage VIN. A code stored in the selection register 28 makes it possible to select either the non-scaled input or one of the down-scaled replicas which best fit in each case. This solution has a number of disadvantages. First of all, the divider is a load for the generator of the signal to be converted, so that, this solution cannot be used with high impedance signal generators; furthermore, when usable, it causes an additional power consumption. In this case a compromise should be taken in selecting the overall resistance of the divider, since the overall resistance should be as high as possible to reduce power consumption, but should be low enough not to limit the charging speed of the capacitor array and therefore the conversion speed. In addition, an error component due to the noise associated with the resistor arrangement adds to the input signal, thereby reducing the accuracy and linearity of the converter. Finally, the difficulty in designing resistors which provide accurate scaling of the input signal and the integrated circuit area needed for the voltage divider should be also taken into account.
To avoid that a current is drawn from the generator of the signal to be converted, a scaling arrangement 26xe2x80x2, as shown in FIG. 3, has been proposed. In this arrangement the input signal VIN is applied to the non-inverting input of an operation amplifier 29. A voltage divider comprising four resistors R0xe2x80x2, R1xe2x80x2, R2xe2x80x2, R3xe2x80x2 is connected as shown to the inverting input of the operation amplifier 29 through a switch SWSxe2x80x2 controlled by a selection register 28xe2x80x2. A feed-back resistor RF is connected between the output and the inverting input of operation amplifier 29. The input signal VIN can be down-scaled by changing the resistance between the inverting input and ground, and thus the gain of the operation amplifier, by means of a digital code stored in the selection register 28xe2x80x2. This arrangement has most of the disadvantages of the arrangement shown in FIG. 2 and additional problems related with the offset, noise and pass-band of the operation amplifier.
A further limitation of the solutions shown in FIGS. 2 and 3 is that the number of possible dynamic ranges is determined by the number of resistors of the voltage divider (typically 4 to 8), so that the user is not free to select the better dynamic range for his application, but is compelled to select one of the available dynamic ranges.
An embodiment of the present invention provides an improved method of operating a SAR-type ADC to match the dynamic range of a voltage signal to be converted with the full scale range of the ADC without the limitations of the prior art converters.
The SAR-type analog-to-digital converter includes an array of binary weighted capacitors, and the method includes the steps of:
obtaining a digital gain code which represents the ratio between the full scale range and the dynamic range of the voltage signal to be converted,
applying the voltage signal to be converted to the capacitor array, so as to charge with the voltage signal to be converted those array capacitors having the same binary weights as the bits of the gain code which have a selected binary value, and
selectively coupling the capacitors of the array to either one of the first and second voltage reference terminals according to the SAR technique, to obtain an output digital code corresponding to the input voltage signal.
Another embodiment of the invention provides an SAR-type ADC that is operated according the improved method.
The SAR-type analog-to-digital converter for converting an input voltage, referred to a common reference terminal, to an output digital code, comprises
a reference voltage generator having a first and second reference voltage terminals,
an array of binary weighted capacitors, each of said capacitors having a first electrode connected to a common node and a second electrode selectively connectable through respective controlled switching means to an input terminal at which the input voltage is applied, to the common reference terminal, or to either one of the first and second reference voltage terminals,
a register for storing a digital gain code,
control means coupled to the controlled switching means to open or close selectively the controllable switching means for connecting in a first step the capacitors of the array either to the input terminal or to the common reference terminal to charge to the voltage signal to be converted only those array capacitors having the same binary weights as the bits of the gain code which have a selected binary value and for connecting in a second step the array capacitors to either one of the first and second reference voltage terminals according to the SAR technique.